1架构SPI NAND 驱动架构SPI 总线↓SPI NAND 驱动 (spi-nand-core.c)├── 实现 spi_driver├── 注册到 SPI 总线└── 在 probe 中↓MTD NAND 核心层 (nand_base.c)↓NAND 芯片驱动 (spi-nand-chip.c)2初始化int rtknflash_ops_init(struct rtknflash *rtkn) { int err; #if !defined(__RTK_BOOT__) /* basic */ rtkn-nand_chip-select_chip rtknflash_ops_select_chip; rtkn-nand_chip-cmdfunc rtknflash_ops_cmdfunc; rtkn-nand_chip-waitfunc rtknflash_wait; rtkn-nand_chip-read_byte rtknflash_ops_read_byte; #if 0 rtkn-nand_chip.read_buf rtknflash_ops_read_buf; rtkn-nand_chip.write_buf rtknflash_ops_write_buf; #endif /* bbt */ #if defined(CONFIG_RTK_REMAP_BBT) || defined(CONFIG_RTK_NORMAL_BBT) rtkn-nand_chip-scan_bbt rtkn_scan_bbt; rtkn-nand_chip-block_bad rtkn_block_bad; rtkn-nand_chip-block_markbad rtkn_block_markbad; #else /* use default bbt: not support */ rtkn-nand_chip-bbt_options NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; #endif /* ecc */ rtkn-nand_chip-ecc.read_page rtkn_ecc_read_page; rtkn-nand_chip-ecc.write_page rtkn_ecc_write_page; rtkn-nand_chip-ecc.read_oob rtkn_ecc_read_oob; rtkn-nand_chip-ecc.write_oob rtkn_ecc_write_oob; /* raw function */ rtkn-nand_chip-ecc.read_page_raw rtkn_ecc_read_page; rtkn-nand_chip-ecc.write_page_raw rtkn_ecc_write_page; /* ecc mode */ rtkn-nand_chip-ecc.mode NAND_ECC_HW; rtkn-nand_chip-ecc.size 1; #if LINUX_VERSION_CODE KERNEL_VERSION(3,10,0) rtkn-nand_chip-ecc.strength 8; #endif /* 8k page */ #if CONFIG_MTD_NAND_RTK_PAGE_SIZE8192 rtkn-nand_chip-ecc.layout nand_bch_oob_256; #endif /* 4k page */ #if CONFIG_MTD_NAND_RTK_PAGE_SIZE4096 rtkn-nand_chip-ecc.layout nand_bch_oob_128; #endif /* 2k page */ #if CONFIG_MTD_NAND_RTK_PAGE_SIZE2048 rtkn-nand_chip-ecc.layout nand_bch_oob_64; #endif /* chip option */ rtkn-nand_chip-options | NAND_NO_SUBPAGE_WRITE; /* for 2.6.30 kernel used */ #if LINUX_VERSION_CODE KERNEL_VERSION(3,10,0) rtkn-nand_chip-options | NAND_NO_AUTOINCR; #endif #endif /* Enable NAND flash access */ err rtk_nand_register_init(); if(err){ pr_err(Error; nand flash register init fail\n); goto exit; } /* Scan NAND */ err nand_scan(rtkn-mtd,1); if (err) { pr_err(Could not scan NAND flash: %d\n, err); goto exit; } exit: return err; }nand_scanint nand_scan(struct mtd_info *mtd, int maxchips) { int ret; ret nand_scan_ident(mtd, maxchips, NULL); if (!ret) ret nand_scan_tail(mtd); return ret; } EXPORT_SYMBOL(nand_scan);nandint nand_scan_ident(struct mtd_info *mtd, int maxchips, struct nand_flash_dev *table) { int i, nand_maf_id, nand_dev_id; struct nand_chip *chip mtd-priv; struct nand_flash_dev *type; int ret; if (chip-flash_node) { ret nand_dt_init(mtd, chip, chip-flash_node); if (ret) return ret; } if (!mtd-name mtd-dev.parent) mtd-name dev_name(mtd-dev.parent); /* Set the default functions */ nand_set_defaults(chip, chip-options NAND_BUSWIDTH_16); /* Read the flash type */ type nand_get_flash_type(mtd, chip, nand_maf_id, nand_dev_id, table); if (IS_ERR(type)) { if (!(chip-options NAND_SCAN_SILENT_NODEV)) pr_warn(No NAND device found\n); chip-select_chip(mtd, -1); return PTR_ERR(type); } chip-select_chip(mtd, -1); /* Check for a chip array */ for (i 1; i maxchips; i) { chip-select_chip(mtd, i); /* See comment in nand_get_flash_type for reset */ chip-cmdfunc(mtd, NAND_CMD_RESET, -1, -1); /* Send the command for reading device ID */ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ if (nand_maf_id ! chip-read_byte(mtd) || nand_dev_id ! chip-read_byte(mtd)) { chip-select_chip(mtd, -1); break; } chip-select_chip(mtd, -1); } if (i 1) pr_info(%d chips detected\n, i); /* Store the number of chips and calc total size for mtd */ chip-numchips i; mtd-size i * chip-chipsize; return 0; }nandstatic struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) { int busw; int i, maf_idx; u8 id_data[8]; /* Select the device */ chip-select_chip(mtd, 0); /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) * after power-up. */ chip-cmdfunc(mtd, NAND_CMD_RESET, -1, -1); /* Send the command for reading device ID */ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ *maf_id chip-read_byte(mtd); *dev_id chip-read_byte(mtd); /* * Try again to make sure, as some systems the bus-hold or other * interface concerns can cause random data which looks like a * possibly credible NAND flash to appear. If the two results do * not match, ignore the device completely. */ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read entire ID string */ for (i 0; i 8; i) id_data[i] chip-read_byte(mtd); if (id_data[0] ! *maf_id || id_data[1] ! *dev_id) { pr_info(second ID read did not match %02x,%02x against %02x,%02x\n, *maf_id, *dev_id, id_data[0], id_data[1]); return ERR_PTR(-ENODEV); } if (!type) type nand_flash_ids; for (; type-name ! NULL; type) { if (is_full_id_nand(type)) { if (find_full_id_nand(mtd, chip, type, id_data, busw)) goto ident_done; } else if (*dev_id type-dev_id) { break; } } chip-onfi_version 0; if (!type-name || !type-pagesize) { /* Check if the chip is ONFI compliant */ if (nand_flash_detect_onfi(mtd, chip, busw)) goto ident_done; /* Check if the chip is JEDEC compliant */ if (nand_flash_detect_jedec(mtd, chip, busw)) goto ident_done; } if (!type-name) return ERR_PTR(-ENODEV); if (!mtd-name) mtd-name type-name; chip-chipsize (uint64_t)type-chipsize 20; if (!type-pagesize) { /* Decode parameters from extended ID */ nand_decode_ext_id(mtd, chip, id_data, busw); } else { nand_decode_id(mtd, chip, type, id_data, busw); } /* Get chip options */ chip-options | type-options; /* * Check if chip is not a Samsung device. Do not clear the * options for chips which do not have an extended id. */ if (*maf_id ! NAND_MFR_SAMSUNG !type-pagesize) chip-options ~NAND_SAMSUNG_LP_OPTIONS; ident_done: /* Try to identify manufacturer */ for (maf_idx 0; nand_manuf_ids[maf_idx].id ! 0x0; maf_idx) { if (nand_manuf_ids[maf_idx].id *maf_id) break; } if (chip-options NAND_BUSWIDTH_AUTO) { WARN_ON(chip-options NAND_BUSWIDTH_16); chip-options | busw; nand_set_defaults(chip, busw); } else if (busw ! (chip-options NAND_BUSWIDTH_16)) { /* * Check, if buswidth is correct. Hardware drivers should set * chip correct! */ pr_info(device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n, *maf_id, *dev_id); pr_info(%s %s\n, nand_manuf_ids[maf_idx].name, mtd-name); pr_warn(bus width %d instead %d bit\n, (chip-options NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); return ERR_PTR(-EINVAL); } nand_decode_bbm_options(mtd, chip, id_data); /* Calculate the address shift from the page size */ chip-page_shift ffs(mtd-writesize) - 1; /* Convert chipsize to number of pages per chip -1 */ chip-pagemask (chip-chipsize chip-page_shift) - 1; chip-bbt_erase_shift chip-phys_erase_shift ffs(mtd-erasesize) - 1; if (chip-chipsize 0xffffffff) chip-chip_shift ffs((unsigned)chip-chipsize) - 1; else { chip-chip_shift ffs((unsigned)(chip-chipsize 32)); chip-chip_shift 32 - 1; } chip-badblockbits 8; chip-erase single_erase; /* Do not replace user supplied command function! */ if (mtd-writesize 512 chip-cmdfunc nand_command) chip-cmdfunc nand_command_lp; pr_info(device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n, *maf_id, *dev_id); if (chip-onfi_version) pr_info(%s %s\n, nand_manuf_ids[maf_idx].name, chip-onfi_params.model); else if (chip-jedec_version) pr_info(%s %s\n, nand_manuf_ids[maf_idx].name, chip-jedec_params.model); else pr_info(%s %s\n, nand_manuf_ids[maf_idx].name, type-name); pr_info(%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n, (int)(chip-chipsize 20), nand_is_slc(chip) ? SLC : MLC, mtd-erasesize 10, mtd-writesize, mtd-oobsize); return type; }/* * NAND Flash Manufacturer ID Codes */ #define NAND_MFR_TOSHIBA 0x98 #define NAND_MFR_SAMSUNG 0xec #define NAND_MFR_FUJITSU 0x04 #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 #define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c #define NAND_MFR_AMD 0x01 #define NAND_MFR_MACRONIX 0xc2 #define NAND_MFR_EON 0x92 #define NAND_MFR_SANDISK 0x45 #define NAND_MFR_INTEL 0x89 #define NAND_MFR_ATO 0x9b #define NAND_MFR_DOSILICON 0xe5 #define NAND_MFR_ESMT 0xc8 /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] { {NAND_MFR_TOSHIBA, Toshiba}, {NAND_MFR_SAMSUNG, Samsung}, {NAND_MFR_FUJITSU, Fujitsu}, {NAND_MFR_NATIONAL, National}, {NAND_MFR_RENESAS, Renesas}, {NAND_MFR_STMICRO, ST Micro}, {NAND_MFR_HYNIX, Hynix}, {NAND_MFR_MICRON, Micron}, {NAND_MFR_AMD, AMD/Spansion}, {NAND_MFR_MACRONIX, Macronix}, {NAND_MFR_EON, Eon}, {NAND_MFR_SANDISK, SanDisk}, {NAND_MFR_INTEL, Intel}, {NAND_MFR_ATO, ATO}, {NAND_MFR_DOSILICON, Dosilicon}, {NAND_MFR_ESMT, Esmt}, {0x0, Unknown} };struct nand_flash_dev nand_flash_ids[] { /* * Some incompatible NAND chips share device IDs and so must be * listed by full ID. We list them first so that we can easily identify * the most specific match. */ {TC58NVG0S3E 1G 3.3V 8-bit, { .id {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), 2 }, {TC58NVG2S0F 4G 3.3V 8-bit, { .id {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, {TC58NVG3S0F 8G 3.3V 8-bit, { .id {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} }, SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, {TC58NVG5D2 32G 3.3V 8-bit, { .id {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} }, SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, {TC58NVG6D2 64G 3.3V 8-bit, { .id {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} }, SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, {SDTNRGAMA 64G 3.3V 8-bit, { .id {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, {H27UCG8T2ATR-BC 64G 3.3V 8-bit, { .id {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), 4 }, /* spi nand support */ /* winbond */ {W25M01GV 1G SPI NAND, { .id {0xef, 0xaa, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 3, 64,NAND_ECC_INFO(6, SZ_512)}, /* esmt */ {ESMT F50L1G41A 1G SPI NAND, { .id {0xc8, 0x21, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 3, 64,NAND_ECC_INFO(6, SZ_512)}, {ESMT F50L1G41B 1G SPI NAND, { .id {0xc8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(6, SZ_512)}, /* mxic */ {MXIC MX35LF1GE4AB 1G SPI NAND, { .id {0xc2, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(6, SZ_512)}, /* HY add by ly*/ {HY HYF1GQ4UDACAE 1G SPI NAND, { .id {0xc9, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(6, SZ_512)}, /* gigadevice */ {GD GD5F1GQ4U 1G SPI NAND, { .id {0xc8, 0xd1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(6, SZ_512)}, {GD GD5F1GQ5UEY 1G SPI NAND, { .id {0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(4, SZ_512)}, #if 0 /* Etron spi nand */ {Etron EM73C044SNB 1G SPI NAND, { .id {0xd5, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64}, #endif //Dosilicon {Dosilicon DS35Q1GAxB 1G SPI NAND, { .id {0xe5, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(4, SZ_512)}, //KIOXIA {KIOXIA TC58CVG0S3HRAIJ 1G SPI NAND, { .id {0x98, 0xe2, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 3, 64,NAND_ECC_INFO(8, SZ_512)}, //toshiba {TOSHIBA TC58CVG0S3HxAIx 1G SPI NAND, { .id {0x98, 0xc2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(8, SZ_512)}, //micron {MICRON MT29F1G01ABA 1G SPI NAND, { .id {0x2C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, SZ_2K, SZ_128, SZ_128K, 0, 2, 64,NAND_ECC_INFO(8, SZ_512)}, LEGACY_ID_NAND(NAND 4MiB 5V 8-bit, 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND(NAND 4MiB 3,3V 8-bit, 0xE3, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND(NAND 4MiB 3,3V 8-bit, 0xE5, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND(NAND 8MiB 3,3V 8-bit, 0xD6, 8, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND(NAND 8MiB 3,3V 8-bit, 0xE6, 8, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND(NAND 16MiB 1,8V 8-bit, 0x33, 16, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 16MiB 3,3V 8-bit, 0x73, 16, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 16MiB 1,8V 16-bit, 0x43, 16, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 16MiB 3,3V 16-bit, 0x53, 16, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 32MiB 1,8V 8-bit, 0x35, 32, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 32MiB 3,3V 8-bit, 0x75, 32, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 32MiB 1,8V 16-bit, 0x45, 32, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 32MiB 3,3V 16-bit, 0x55, 32, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 64MiB 1,8V 8-bit, 0x36, 64, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 64MiB 3,3V 8-bit, 0x76, 64, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 64MiB 1,8V 16-bit, 0x46, 64, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 64MiB 3,3V 16-bit, 0x56, 64, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 128MiB 1,8V 8-bit, 0x78, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 128MiB 1,8V 8-bit, 0x39, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 128MiB 3,3V 8-bit, 0x79, 128, SZ_16K, SP_OPTIONS), LEGACY_ID_NAND(NAND 128MiB 1,8V 16-bit, 0x72, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 128MiB 1,8V 16-bit, 0x49, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 128MiB 3,3V 16-bit, 0x74, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 128MiB 3,3V 16-bit, 0x59, 128, SZ_16K, SP_OPTIONS16), LEGACY_ID_NAND(NAND 256MiB 3,3V 8-bit, 0x71, 256, SZ_16K, SP_OPTIONS), /* * These are the new chips with large page size. Their page size and * eraseblock size are determined from the extended ID bytes. */ /* 512 Megabit */ EXTENDED_ID_NAND(NAND 64MiB 1,8V 8-bit, 0xA2, 64, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64MiB 1,8V 8-bit, 0xA0, 64, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64MiB 3,3V 8-bit, 0xF2, 64, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64MiB 3,3V 8-bit, 0xD0, 64, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64MiB 3,3V 8-bit, 0xF0, 64, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64MiB 1,8V 16-bit, 0xB2, 64, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 64MiB 1,8V 16-bit, 0xB0, 64, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 64MiB 3,3V 16-bit, 0xC2, 64, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 64MiB 3,3V 16-bit, 0xC0, 64, LP_OPTIONS16), /* 1 Gigabit */ EXTENDED_ID_NAND(NAND 128MiB 1,8V 8-bit, 0xA1, 128, LP_OPTIONS), EXTENDED_ID_NAND(NAND 128MiB 3,3V 8-bit, 0xF1, 128, LP_OPTIONS), EXTENDED_ID_NAND(NAND 128MiB 3,3V 8-bit, 0xD1, 128, LP_OPTIONS), EXTENDED_ID_NAND(NAND 128MiB 1,8V 16-bit, 0xB1, 128, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 128MiB 3,3V 16-bit, 0xC1, 128, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 128MiB 1,8V 16-bit, 0xAD, 128, LP_OPTIONS16), /* 2 Gigabit */ EXTENDED_ID_NAND(NAND 256MiB 1,8V 8-bit, 0xAA, 256, LP_OPTIONS), EXTENDED_ID_NAND(NAND 256MiB 3,3V 8-bit, 0xDA, 256, LP_OPTIONS), EXTENDED_ID_NAND(NAND 256MiB 1,8V 16-bit, 0xBA, 256, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 256MiB 3,3V 16-bit, 0xCA, 256, LP_OPTIONS16), /* 4 Gigabit */ EXTENDED_ID_NAND(NAND 512MiB 1,8V 8-bit, 0xAC, 512, LP_OPTIONS), EXTENDED_ID_NAND(NAND 512MiB 3,3V 8-bit, 0xDC, 512, LP_OPTIONS), EXTENDED_ID_NAND(NAND 512MiB 1,8V 16-bit, 0xBC, 512, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 512MiB 3,3V 16-bit, 0xCC, 512, LP_OPTIONS16), /* 8 Gigabit */ EXTENDED_ID_NAND(NAND 1GiB 1,8V 8-bit, 0xA3, 1024, LP_OPTIONS), EXTENDED_ID_NAND(NAND 1GiB 3,3V 8-bit, 0xD3, 1024, LP_OPTIONS), EXTENDED_ID_NAND(NAND 1GiB 1,8V 16-bit, 0xB3, 1024, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 1GiB 3,3V 16-bit, 0xC3, 1024, LP_OPTIONS16), /* 16 Gigabit */ EXTENDED_ID_NAND(NAND 2GiB 1,8V 8-bit, 0xA5, 2048, LP_OPTIONS), EXTENDED_ID_NAND(NAND 2GiB 3,3V 8-bit, 0xD5, 2048, LP_OPTIONS), EXTENDED_ID_NAND(NAND 2GiB 1,8V 16-bit, 0xB5, 2048, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 2GiB 3,3V 16-bit, 0xC5, 2048, LP_OPTIONS16), /* 32 Gigabit */ EXTENDED_ID_NAND(NAND 4GiB 1,8V 8-bit, 0xA7, 4096, LP_OPTIONS), EXTENDED_ID_NAND(NAND 4GiB 3,3V 8-bit, 0xD7, 4096, LP_OPTIONS), EXTENDED_ID_NAND(NAND 4GiB 1,8V 16-bit, 0xB7, 4096, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 4GiB 3,3V 16-bit, 0xC7, 4096, LP_OPTIONS16), /* 64 Gigabit */ EXTENDED_ID_NAND(NAND 8GiB 1,8V 8-bit, 0xAE, 8192, LP_OPTIONS), EXTENDED_ID_NAND(NAND 8GiB 3,3V 8-bit, 0xDE, 8192, LP_OPTIONS), EXTENDED_ID_NAND(NAND 8GiB 1,8V 16-bit, 0xBE, 8192, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 8GiB 3,3V 16-bit, 0xCE, 8192, LP_OPTIONS16), /* 128 Gigabit */ EXTENDED_ID_NAND(NAND 16GiB 1,8V 8-bit, 0x1A, 16384, LP_OPTIONS), EXTENDED_ID_NAND(NAND 16GiB 3,3V 8-bit, 0x3A, 16384, LP_OPTIONS), EXTENDED_ID_NAND(NAND 16GiB 1,8V 16-bit, 0x2A, 16384, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 16GiB 3,3V 16-bit, 0x4A, 16384, LP_OPTIONS16), /* 256 Gigabit */ EXTENDED_ID_NAND(NAND 32GiB 1,8V 8-bit, 0x1C, 32768, LP_OPTIONS), EXTENDED_ID_NAND(NAND 32GiB 3,3V 8-bit, 0x3C, 32768, LP_OPTIONS), EXTENDED_ID_NAND(NAND 32GiB 1,8V 16-bit, 0x2C, 32768, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 32GiB 3,3V 16-bit, 0x4C, 32768, LP_OPTIONS16), /* 512 Gigabit */ EXTENDED_ID_NAND(NAND 64GiB 1,8V 8-bit, 0x1E, 65536, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64GiB 3,3V 8-bit, 0x3E, 65536, LP_OPTIONS), EXTENDED_ID_NAND(NAND 64GiB 1,8V 16-bit, 0x2E, 65536, LP_OPTIONS16), EXTENDED_ID_NAND(NAND 64GiB 3,3V 16-bit, 0x4E, 65536, LP_OPTIONS16), {NULL} };rtknflash_ops_init-nand_scan-nand_scan_ident-nand_get_flash_type-nand_flash_ids(结构体里面有nand_maf_id和nand_dev_id的匹配匹配一致才能注册/* Read manufacturer and device IDs */ *maf_id chip-read_byte(mtd); *dev_id chip-read_byte(mtd);